Quad Tile Intel Xe-HP GPU

At very last week’s Intel Architecture Day, Intel’s main architect, Raja Koduri, briefly held up the smallest member of the company’s forthcoming Xe-HP series of server CPUs, the just one tile configuration. Now, only a handful of times later on, he has upped the ante by showing off the largest, four tile configuration.

Created to be a scalable chip architecture, Xe-HP is set to be out there with one, two, or 4 tiles. And whilst Intel has however to disclose too much in the way of particulars on the architecture, centered on their packaging disclosures it looks like the company is employing their EMIB tech to wire up the GPU tiles, as nicely as the GPU’s on-package deal HBM memory.

Assuming it can make it to sector, a multi-tiled GPU – in essence numerous GPUs in a one package deal – would be a major accomplishment for Intel. GPUs are notoriously bandwidth-hungry due to the need to have to shovel info about among cores, caches, and command frontends, which can make them non-trivial to split up in a chiplet/tiled manner. Even if Intel can only use this sort of multi-tile scalability for compute workloads, that would have a major effects on what form of overall performance a solitary GPU package can achieve, and how long run servers may be developed.